(Processing Systems Lab)

Jul 01, 2017

Fahim's computational-locked PLL at VLSI Symposium 2017.

Fahim's paper on Computational Locking, a fundamentally different way of locking PLLs was presented at the Symposium on VLSI circuits in Kyoto, Japan this June. The paper demonstrates how advances in computing, coupled with a fresh-look at the phenomenon of phase and frequency acquisition can yield unprecedented lock performance - with silicon measured re-lock and cold-start lock times five times lower than the state of the art for system clocking.