(Processing Systems Lab)


Resonant clocking has emerged as a promising approach for achieving energy-efficiency in high-performance digital systems. However, the limited frequency range of efficient resonant clocking operation restricts its applicability in widely-used Dynamic Voltage and Frequency Scaling (DVFS) systems. Existing frequency-scalable resonant clocking implementations are either not voltage-scalable, or provide only modest frequency range extension. This paper presents a true voltage and frequency-scalable quasi-resonant clock architecture. Simulations on a 64-bit pipelined multiply-accumulate unit in 65nm CMOS demonstrate continuous frequency scalability over 2MHz–200MHz. Efficient operation during dynamic voltage frequency-scaling is demonstrated over 0.8V-1.3V, resulting in a 54% energy-per cycle reduction over conventional distributions.