Next-Generation Clocking¶

Clocking remains one of the most challengeing and impactful areas in modern SoC design, from high-performance server-class processors, to ultra-low power IoT systems. Over the past decade, several new challenges have emerged in the area of clocking including:

• Low-voltage operation, to near-threshold and sub-threshold voltages
• Robust, low-power clock distribution for DVFS systems with wide tuning ranges
• The need for rapid re-lock and cold-start times for system-clocking, wireless, and wireline applications
• Synchronization and domain crossing between across multiple clock domains in heterogeneous systems

PSyLab has been actively focussed on making a dent in these areas through efforts on:

1. Design of all-digital PLLs with dramatically improved lock-times
2. Design of resonant clock distributions capable of supporting continuous DVFS