(Processing Systems Lab)

Integrated Power and Voltage Regulation

On account of origins, a good number of projects, both past and present revolve around integrated power conversion and voltage regulation. Instead of focusing on developing the next better buck converter or switched capacitor converter design, we instead focus on cross-pollinating ideas in control, computing and co-design to address important challenges in the area.

For instance, instead of trying to design even faster voltage regulation circuitry, we instead proposed the Unified Clock and Power Architecture (UniCaP) which observes that voltage-regulation in digital systems is motivated by the need to maintain timing slack. Thus, both clock and voltage regulation loops are combined into a single regulation loop, allowing the system to adapt to a voltage droop through (near) instantaneous clock frequency modulation while at the same time, regulating system performance. The result is a system that nearly eliminates supply voltage guardbands while continuing to regulate system performance.

We have applied ideas in computational control and runtime optimization to integrated regulation and ultra low power design as well. Examples of this are recent work on computationally controlled LDOs, and in computationally enabled minimum energy computing while continuing to provide minimum performance guarantees.

More details on this work can be found here:

  1. UniCaP, both buck and switched-capacitor architectures.

  2. Computational LDO regulation

  3. Computationally enabled minimum-energy-point tracking