While the control systems community has long moved past traditional PID control, we in hardware design, have be a little slower in keeping pace with their advances. A significant portion of low-latency hardware control continues to rely on essentially PID control.
There are several good reasons for the status-quo. PID control is relatively computationally non-intensive and can be performed very quickly, essential for applications requiring fast response times. Digital computing capabilities have evolved however, prompting a relook at these systems. We have been exploring the idea of computational control recently. The basic idea is straightforward : Apply more aggressive control approaches to hardware systems, and exploit advances in digital computation efficiency and throughput over the years, as well as other standard hardware optimizations (e.g. signal flow graph transformations) to significantly enhance the performance of these control systems.
Our recent work has focused on two of the most commonly encountered modules, PLLs and LDOs:
Computationally locked PLL design views the action of phase-lock acquisition as an optimization problem and performs a number of reduced precision calculations to solve for the Digitally Controlled Oscillator (DCO) sequence that will achieve robust lock as rapidly as possible.
Computational LDO regulation is a (very simplified, for now) take on model predictive control that relies on a time-domain model of the regulator, capable of capturing loop-delays, non-linearities and all, and evaluating this model every cycle to achieve rapid, stable response regardless of PVT variations especially brought upon by the wide operating range of Vin, Vout and temperature.