Research Areas
Individual Projects
Computationally locked PLLs
Reducing PLL lock time for cold-start and relock by an order of magnitude.
Buck converter UniCAP
Demonstrating Unified Clock And Power architecture with a high-performance buck converter.
Quasi-resonant clocking
Augmenting resonant clocking design with dynamic frequency and voltage scaling capabilities.
Buck converter UniCAP
Demonstrating Unified Clock And Power architecture with a high-performance buck converter.
Switched-capacitor UniCAP
Demonstrating Unified Clock And Power architecture with a low-voltage switched-capacitor integrated voltage regulator.
Computationally controlled LDOs
A (significantly) simplified Model Predicitive Control approach to optimizing regulator dynamics
Computationally Enabled Digital Minimum Energy Point Tracking
A digital technique to determine total energy consumed per computation, inclusive of regulator losses, and dynamically set supply-voltage for minimum energy dissipation subject to minimum performance requirements
On-chip power supply measurement
Techniques for measuring on-chip supply noise with millivolt resolution and multi-GHz bandwidth.
High-density neural signal recording
A multiplexed neural-recording front-end that exploits neural-signal statistics to achieve a robust architecture with 10X improvement in neural recording density.
MATIC
Learning around failures in low-voltage on-chip memories to enable energy-efficient neural network accelerators.
Computationally controlled LDOs
A (significantly) simplified Model Predicitive Control approach to optimizing regulator dynamics
Computationally locked PLLs
Reducing PLL lock time for cold-start and relock by an order of magnitude.
Energy-efficient, Robust True Random Number Generators (TRNGs)
Digital true random-number generation with imperfect entropy sources.