PSyLab

(Processing Systems Lab)

Publications

2019
Sep
A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation
F. Rahman, G. Taylor and V. S. Sathe
JSSC, vol. 54 no. 9, Sep 2019
2019
Sep
A 10b 120MS/s SAR ADC with Reference RippleCancellation Technique
X. Tang, Y. Shen, L. Shen, W. Zhao, Z. Zhu, V. S. Sathe and N. Sun
CICC 2019
2019
Feb
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS
F. Rahman, R. Pamula, A. Boora and V. S. Sathe
ISSCC 2019
2019
Feb
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS
X. Sun, A. Boora, W. Zhang, R. Pamula and V. S. Sathe
ISSCC 2019
2018
Dec
Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors
S. Kim, P. Howe, T. Moreau, A. Alaghi, L. Ceze and V. S. Sathe
Transactions on Circuits and Systems-1
2018
Nov
Architecture Considerations for Stochastic Computing Accelerators
V. Lee, A. Alaghi, R. Pamula, V. S. Sathe, L. Ceze and M. Oskin
Transactions on Computer-Aided Design of Integrated Circuits and Systems
2018
Jun
An all-digital true-random-number generator with integrated de-correlation and bias correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS
R. Pamula, X. Sun, S. Kim, F. Rahman F. Rahman and V. S. Sathe
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
2018
Jun
An all-digital unified clock frequency and switched-capacitor voltage regulator for variation tolerance in a sub-threshold ARM Cortex M0 processor
F. Rahman, S. Kim, N. John, R. Kumar, R. Pamula and V. S. Sathe
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
2018
Jun
Quasi-resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking for DVFS Systems
F. Rahman, and V. S. Sathe
Journal of Solid-State Circuits (JSSC)
2018
Feb
MATIC: Learning Around Errors for Efficient Low-Voltage Neural Network Accelerators
S. Kim, P. Howe, T. Moreau, A. Alaghi, L. Ceze, and V. S. Sathe
Design Automation & Test in Europe Conference & Exhibition (DATE)
2018
Feb
A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor
X. Sun, S. Kim, F. Rahman, R. Pamula, X. Li, N. John, and V. S. Sathe
IEEE International Solid-State Circuits Conference (ISSCC)
2017
Jun
Computational locking: Accelerating lock-times in all-digital PLLs
F. Rahman, G. F. Taylor and V. S. Sathe
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
2017
Jun
A scalable, highly-multiplexed delta-encoded digital feedback ECoG recording amplifier with common and differential-mode artifact suppression
W. A. Smith, J. P. Uehlin, S. I. Perlmutter, J. C. Rudell and V. S. Sathe
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
2017
Jun
Exploring Computation-Communication Tradeoffs in Camera Systems
A. Mazumdar, T. Moreau, S. Kim, M. Cowan, A. Alaghi, L. Ceze, M. Oskin, and V. Sathe
IEEE International Symposium on Workload Characterization (IISWC)
2017
Feb
Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 μW Analog Front End with Reduced ADC Resolution Requirements
William A. Smith, Brian J. Mogen, Eberhard E. Fetz, V. S. Sathe, and Brian P. Otis
IEEE Transactions on Biomedical Circuits and Systems (TBioCAS)
2017
Mar
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing
V. T. Lee, A. Alaghi, J. P. Hayes, V. S. Sathe and L. Ceze
Design Automation & Test in Europe Conference & Exhibition (DATE)
2016
Sep
UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction
S. Gangopadhyay, S. B. Nasir, A. Subramanian, V. S. Sathe, and A. Raychowdhury
IEEE European Solid-State Circuits Conference (ESSCIRC)
2016
Aug
Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip
A. Najafi, J. C. Rudell, and V. S. Sathe
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
May
A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Applications
C. Huang, Y. Chen, T. Zhang, V. S. Sathe, and J. C. Rudell
IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
Feb
Voltage-Scalable Frequency-Independent Quasi-Resonant Clocking Implementation of a 0.7-to-1.2V DVFS System
F. U. Rahman, and V. S. Sathe
IEEE International Solid-State Circuits Conference (ISSCC)
2015
Aug
Fully-Integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS
X. Mi, D. Mandal, V. S. Sathe, B. Bakkologlu, and J. Seo
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
2015
Aug
Analysis and optimization of CMOS switched-capacitor converter
V. S. Sathe, and J.Seo
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
2014
Aug
Quasi-Resonant Clocking : A Run-time Control Approach for True Voltage-Frequency-Scalability
V. S. Sathe
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
2014
Aug
A deterministic-dither-based, all-digital system for on-chip power supply noise measurement
K. Sankaragomathi, W. A. Smith and V. S Sathe
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
2013
Jun
Inductor Design for Global Resonant Clock Distribution
V. S. Sathe, A. Loke, T. Khan, V. Ross, A. Raman, G. Vandevalk, P. Papadopoulos and N. Provatas
ACM/EDAC/IEEE Design Automation Conference (DAC)
Jan
Resonant Clock Design for a Power-efficient, High-volume x86-64 Microprocessor
V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. C. Papaefthymiou, and S. Naffziger
Journal of Solid-State Circuits (JSSC), Special Issue on ISSCC‘12 (invited paper)
2012
Feb
Resonant clock design for a power-efficient, high-volume x86-64 microprocessor
V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. Papaefthymiou and S. Naffziger
IEEE International Solid-State Circuits Conference (ISSCC)
2010
Apr.
187MHz subthreshold-supply charge-recovery FIR
W. S. Ma, J. C. Kao, V. S. Sathe, and M. C. Papaefthymiou
Journal of Solid-State Circuits (JSSC), Special Issue on 2009 Symposium on VLSI Circuits (invited paper)
Feb
A 32nm fully-integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency
H.-P. Le, M. Seeman, S. Sanders, V. S. Sathe, S. Naffziger, and E. Alon
IEEE International Solid-State Circuits Conference (ISSCC)
2009
Sep
A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead
J. C. Kao, W. S. Ma, V. S. Sathe, and M. C. Papaefthymiou
IEEE European Solid-State Circuits Conference (ESSCIRC)
2009
Sep
A resonant-clock 200MHz ARM926EJ-S™ microcontroller
M. C. Papaefthymiou, A. Ishii, J. Kao., and V. S. Sathe
IEEE European Solid-State Circuits Conference (ESSCIRC)
Jun
A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic
W. S. Ma, J. C. Kao, V. S. Sathe, and M. C. Papaefthymiou
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
Apr
Resonant-clock latch-based design
V. S. Sathe, J. Kao and M. C. Papaefthymiou
Journal of Solid-State Circuits (JSSC), Special Issue on 2007 Symposium on VLSI Circuits (invited paper)
2007
Sep
A 0.8-1.2GHz single-phase resonant-clocked FIR filter with level-sensitive latches
V. S. Sathe, J. C. Kao, and M. C. Papaefthymiou
IEEE Custom Integrated Circuits Conference (CICC)
Jun
RF2: A 1GHz FIR filter with distributed resonant clock generator
V. S. Sathe, J. C. Kao, and M. C. Papaefthymiou
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
Apr
On-chip synchronous communication between clock domains with quotient frequencies
V. S. Sathe, M. C. Papaefthymiou, S. V. Kosonocky, and S. Kim
Electronics Letters, vol. 43, no. 9, pp. 497–499, Apr. 2007.
Jan
Energy-efficient GHz-class charge-recovery logic
V. S. Sathe, J.-Y. Chueh, and M. C. Papaefthymiou
Journal of Solid-State Circuits (JSSC), Special Issue on ISSCC‘06 (invited paper).
2006
Sep
900MHz to 1.2GHz two-phase resonant clock network with programmable driver and loading
J.-Y. Chueh, V. S. Sathe, and M. C. Papaefthymiou
IEEE Custom Integrated Circuits Conference (CICC)
Feb
A 1.1GHz charge-recovery logic
V. S. Sathe, J-Y. Chueh, and M. C. Papaefthymiou
IEEE International Solid-State Circuits Conference (ISSCC)
2005
Aug
A GHz-class charge-recovery logic
V. S. Sathe, C. H. Ziesler, and M. C. Papaefthymiou
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
May
Fast, efficient, recovering and irreversible
V. S. Sathe, J-Y. Chueh, J. Kim, C.H. Ziesler, S. Kim, and M. C. Papaefthymiou
Conference on Computing Frontiers, pp. 407–413, Ischia, Italy, 2005.
May
Two-phase resonant clock distribution
J-Y. Chueh, V. S. Sathe and M. C. Papaefthymiou
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 65–70, Tampa, FL, 2005.
May
Boost logic: A high-speed energy-recovery circuit family
V. S. Sathe, C. H. Ziesler and M. C. Papaefthymiou
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
2004
Sep
A synchronous interface for SoCs with multiple clock domains
V. S. Sathe, S. Kim, S. Kosonocky, and M. C. Papaefthymiou
IEEE International System-on-Chip Conference (SOCC)
2003
Aug
A 225 MHz resonant clocked ASIC
C. H. Ziesler, J. Kim , V. S. Sathe and M. C. Papaefthymiou
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)