Publications
2022
Feb

Energy Minimization of Duty Cycled Domains through Domain Decoupling Capacitance Energy Recycling and Autonomous Energy Tracking
ISSCC 2022
Feb

An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS
ISSCC 2022
2021
Apr

A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation
CICC 2021
Feb

A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS
ISSCC 2021
Feb

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS
VLSI Symposium 2020
2020
Jul

A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS
JSSC, vol. 55, no. 7, Jul. 2020
Jun

Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS
VLSI Symposium 2020
Sep

A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation
JSSC, vol. 54 no. 9, Sep 2019
2019
Sep

A 10b 120MS/s SAR ADC with Reference RippleCancellation Technique
CICC 2019
Feb

Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS
ISSCC 2019
Feb

A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS
ISSCC 2019
2018
Dec

Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors
Transactions on Circuits and Systems-1
Nov

Architecture Considerations for Stochastic Computing Accelerators
Transactions on Computer-Aided Design of Integrated Circuits and Systems
Jun

An all-digital true-random-number generator with integrated de-correlation and bias correction at 3.2-to-86 Mb/s, 2.58 pJ/bit in 65-nm CMOS
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
Jun

An all-digital unified clock frequency and switched-capacitor voltage regulator for variation tolerance in a sub-threshold ARM Cortex M0 processor
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
Jun

Quasi-resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking for DVFS Systems
Journal of Solid-State Circuits (JSSC)
Feb

MATIC: Learning Around Errors for Efficient Low-Voltage Neural Network Accelerators
Design Automation & Test in Europe Conference & Exhibition (DATE)
Feb

A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor
IEEE International Solid-State Circuits Conference (ISSCC)
2017
Jun

Computational locking: Accelerating lock-times in all-digital PLLs
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
Jun

A scalable, highly-multiplexed delta-encoded digital feedback ECoG recording amplifier with common and differential-mode artifact suppression
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
Jun

Exploring Computation-Communication Tradeoffs in Camera Systems
IEEE International Symposium on Workload Characterization (IISWC)
Feb

Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 μW Analog Front End with Reduced ADC Resolution Requirements
IEEE Transactions on Biomedical Circuits and Systems (TBioCAS)
Mar

Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing
Design Automation & Test in Europe Conference & Exhibition (DATE)
2016
Sep

UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction
IEEE European Solid-State Circuits Conference (ESSCIRC)
Aug

Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
May

A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Applications
IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
Feb

Voltage-Scalable Frequency-Independent Quasi-Resonant Clocking Implementation of a 0.7-to-1.2V DVFS System
IEEE International Solid-State Circuits Conference (ISSCC)
2015
Aug

Fully-Integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
Aug

Analysis and optimization of CMOS switched-capacitor converter
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
2014
Aug

Quasi-Resonant Clocking : A Run-time Control Approach for True Voltage-Frequency-Scalability
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
Aug

A deterministic-dither-based, all-digital system for on-chip power supply noise measurement
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
2013
Jun

Inductor Design for Global Resonant Clock Distribution
ACM/EDAC/IEEE Design Automation Conference (DAC)
Jan

Resonant Clock Design for a Power-efficient, High-volume x86-64 Microprocessor
Journal of Solid-State Circuits (JSSC), Special Issue on ISSCC‘12 (invited paper)
2012
Feb

Resonant clock design for a power-efficient, high-volume x86-64 microprocessor
IEEE International Solid-State Circuits Conference (ISSCC)
2010
Apr.

187MHz subthreshold-supply charge-recovery FIR
Journal of Solid-State Circuits (JSSC), Special Issue on 2009 Symposium on VLSI Circuits (invited paper)
Feb

A 32nm fully-integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency
IEEE International Solid-State Circuits Conference (ISSCC)
2009
Sep

A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead
IEEE European Solid-State Circuits Conference (ESSCIRC)
Sep

A resonant-clock 200MHz ARM926EJ-S™ microcontroller
IEEE European Solid-State Circuits Conference (ESSCIRC)
Jun

A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
Apr

Resonant-clock latch-based design
Journal of Solid-State Circuits (JSSC), Special Issue on 2007 Symposium on VLSI Circuits (invited paper)
2007
Sep

A 0.8-1.2GHz single-phase resonant-clocked FIR filter with level-sensitive latches
IEEE Custom Integrated Circuits Conference (CICC)
Jun

RF2: A 1GHz FIR filter with distributed resonant clock generator
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
Apr

On-chip synchronous communication between clock domains with quotient frequencies
Electronics Letters, vol. 43, no. 9, pp. 497–499, Apr. 2007.
Jan

Energy-efficient GHz-class charge-recovery logic
Journal of Solid-State Circuits (JSSC), Special Issue on ISSCC‘06 (invited paper).
2006
Sep

900MHz to 1.2GHz two-phase resonant clock network with programmable driver and loading
IEEE Custom Integrated Circuits Conference (CICC)
Feb

A 1.1GHz charge-recovery logic
IEEE International Solid-State Circuits Conference (ISSCC)
2005
Aug

A GHz-class charge-recovery logic
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)
May

Fast, efficient, recovering and irreversible
Conference on Computing Frontiers, pp. 407–413, Ischia, Italy, 2005.
May

Two-phase resonant clock distribution
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 65–70, Tampa, FL, 2005.
May

Boost logic: A high-speed energy-recovery circuit family
IEEE International Symposium on VLSI Circuits (VLSI-Circuits)
2004
Sep

A synchronous interface for SoCs with multiple clock domains
IEEE International System-on-Chip Conference (SOCC)
2003
Aug

A 225 MHz resonant clocked ASIC
IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED)