PSyLab

(Processing Systems Lab)

Oct 15, 2020

Congratulations to Chi-Hsiang on his paper at ISSCC'21!

Chi-Hsiang will be presenting his paper on a 4-domain Single-Inductor Multiple Output (SIMO) 65nm CMOS test-chip at ISSCC this coming Feb. Integrated Voltage Regulators (IVRs) will continue to play an increasingly important role in future SoCs, enabling fine spatio-temporal Vdd control. Buck converters are the most efficient form of IVR, but they are bulky, affording only a handful of voltage domains. Modern SoCs routinely involve more than a couple dozen voltge domains, resulting in a domain-scalability gap. SIMO converters are a promising alternative, affording Buck-converter efficiencies without additional bulky inductors for each voltage domain. However, SIMO regulators suffer from poor transient response and significant ripple, requiring extensive Vdd margining. This margining wastefully inflates power draw and degrades overall system efficiencies.

Chi-Hsiang's solution explores independent but synergistic approaches to the problem. First, he demonstrates how adaptive clocking effectively tolerates Vdd ripple and droop, dramatically reducing guardbands and boosting system efficiency. However, not all systems are amenable to adaptive clocking. A second technique, Dynamic Droop Allocation (DDA) is presented. DDA represents a departure from traditional SIMO control techniques, performing concurrent and coordinated regulation of all 4 domains instead of a greedy sequential approach that sequentially restores individual voltage domains. This concurrent approach allow the system to dynamically share droop between domains, reducing the worst case impact on each domain.

Stay tuned till Feb. 2021 to see the paper and presentation slides for this work. Congratulations again Chi-Hsiang, on a truly well-deserved outcome!

Jul 15, 2020

Jul 01, 2020

Jun 01, 2020

Congrats to Xun on two VLSI Symposium papers.

Xun presented two papers at VLSI symposium this year. The first is a follow-up on our prior work on the UniCaP architecture, addressing loop bandwidth considerations that are important in high performance computing. Also included was an analysis on the impact of clock insertion delay on achievable margin reductions. Her second paper was the first ever demonstration of Model Predictive Control in integrated buck converters. MPC buck implementations for Integrated Voltage Regulators (IVR) had been previously considered impossible due to the very stringent latency limitations - control must be performed with loop latencies in the single-digit ns range. Existing MPC implementations at the board level employ microprocessors that incur more than 50 microseconds of latency. We employed a modification of the traditional MPC formulation to enable time-optimal control of an IVR buck.

Jan 15, 2019

Congrats to Xun on her paper at ISSCC'19!

Xun recently successfully designed and tested her latest prototype test-chip. The work will be presented in the upcoming ISSCC conference in February.

Xun's latest work revolves around developing the idea of computational control that we have been exploring, and applying it to Low Dropout Regulators for starters. The idea is to construct accurate time-domain state-equations of systems and solve them efficiently at runtime to yield systems with enhanced transient response and stability. The work also demonstrates how low-complexity statistical analysis (1-bit precision) can be used to auto-tune system parameters to compensate for PVT variation, typically a source of much of the required margining that is done in digital LDOs in particular.

Jan 15, 2019

Congrats to Fahim on his paper at ISSCC'19!

Fahim recently successfully designed and tested his latest and last test-chip -- he graduates May 2019 -- which will be presented at ISSCC'19.

Minimum energy tracking is a potentially valuable capability in ultra-low power sensor systems. However, real-world applications need to achieve ideally minimum energy operation while continuing to provide performance guarantees.

Quite often, performance-constrained minimum-energy operation means simply operating at the lowest frequency-voltage point that the application requires. However, in ultra-low power (and yes, performance) applications sometimes, these requirements can fall below the frequency corresponding to the Minimum Energy Point (MEP). At these times, it makes sense for the system whenever possible, to actually operate at a higher voltage and frequency, get more work done more efficiently, and then go to sleep for optimal energy dissipation.

This work demonstrates a system that autonomously seeks the MEP while providing performance guarantees. Moreover, in a departure from prior work, the system uses computational techniques to determine the total energy delivered by the power-source (battery) per computation, which it then seeks to minimize.