(Processing Systems Lab)

Oct 15, 2020

Congratulations to Chi-Hsiang on his paper at ISSCC'21!

Chi-Hsiang will be presenting his paper on a 4-domain Single-Inductor Multiple Output (SIMO) 65nm CMOS test-chip at ISSCC this coming Feb. Integrated Voltage Regulators (IVRs) will continue to play an increasingly important role in future SoCs, enabling fine spatio-temporal Vdd control. Buck converters are the most efficient form of IVR, but they are bulky, affording only a handful of voltage domains. Modern SoCs routinely involve more than a couple dozen voltge domains, resulting in a domain-scalability gap. SIMO converters are a promising alternative, affording Buck-converter efficiencies without additional bulky inductors for each voltage domain. However, SIMO regulators suffer from poor transient response and significant ripple, requiring extensive Vdd margining. This margining wastefully inflates power draw and degrades overall system efficiencies.

Chi-Hsiang's solution explores independent but synergistic approaches to the problem. First, he demonstrates how adaptive clocking effectively tolerates Vdd ripple and droop, dramatically reducing guardbands and boosting system efficiency. However, not all systems are amenable to adaptive clocking. A second technique, Dynamic Droop Allocation (DDA) is presented. DDA represents a departure from traditional SIMO control techniques, performing concurrent and coordinated regulation of all 4 domains instead of a greedy sequential approach that sequentially restores individual voltage domains. This concurrent approach allow the system to dynamically share droop between domains, reducing the worst case impact on each domain.

Stay tuned till Feb. 2021 to see the paper and presentation slides for this work. Congratulations again Chi-Hsiang, on a truly well-deserved outcome!