(Processing Systems Lab)

Oct 15, 2017

Xun's Unified Clock and Power work to be presented at ISSCC 2018

A general Unified Clock and Power (UniCaP) architecture that nearly eliminates supply voltage margins for droop, process (chip-mean) and temperature variation will be presented at ISSCC this coming Feb. Congratulations to Xun, Fahim, Sung, Rajesh, Xi and Naveen.

Instead of the traditional approach of disjoint voltage regulation and clock generation/distribution, UniCaP merges the two systems, allowing voltage droops to be corrected by an "elastic" PLL, and subsuming voltage control into the PLL control loop to recover not only the supply voltage needed to meet timing, but also recover any lost cycles. Demonstrated and characterized using a 65nm ARM Cortex, this approach offers several other advantages beyond enabling true all-digital supply voltage regulation, and virtual elimination of voltage margins: It enables for the first time, the ability to design truly energy-efficient near- and sub-threshold systems while guaranteeing a target performance.