(Processing Systems Lab)

Chip Gallery

A 0.6–1.1V Computationally Regulated Digital LDO with 2.79-cycle Mean Settling Time and Au-tonomous Runtime Gain Tracking in 65-nm CMOS

Xun Sun [ISSCC 2019]

A Combined All-Digital PLL-Buck Slack Regulation System with Autonomous CCM/DCM Transition Control and 82% Average Voltage-Margin Reduction in a 0.6-to-1.0V Cortex-M0 Processor

Xun Sun [ISSCC 2018]

The first demonstration of truly voltage-scalable quasi-resonant clocking.

Fahim U. Rahman [ISSCC]

RF2: The first-ever fully integrated resonant clocked datapath.

Visvesh Sathe [VLSI Symp, JSSC]

Computationally-Enabled Total Energy Minimization under Performance Requirements for a Volt-age Regulated 0.38–¬0.58V Microprocessor in 65nm CMOS

Fahim ur Rahman [ISSCC 2019]

The first-ever demonstration of computational locking for ADPLLs, a radically different way of achieving lock to advance cold-start lock-times by nearly an order of magnitude.

Fahim U. Rahman [ISSCC]

Techniques for "learning around" largely-static memory errors caused by aggressive memory-voltage overscaling, demonstrated on a low-power DNN accelerator SoC.

Sung Kim

RF1: Single-phase resonant clocked ASIC with programmable operating frequency of 0.8GHz-1.2GHz

Visvesh Sathe [CICC, JSSC]

An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor

Fahim ur Rahman [VLSI 2018]

A highly-multiplexed, delta-encoded mixed-signal biopotential recording architecture with common and differential-mode artifact suppression.

William A. Smith [VLSI Symp.]

A prototype demonstrating optimized ECoG signal chain design with reduced noise and ADC requirements, resolved from specific characteristics of ECoG signals.

William A. Smith [ESSCIRC] [TBIOCAS]