(Processing Systems Lab)

Chip Gallery

The first-ever demonstration of computational locking for ADPLLs, a radically different way of achieving lock to advance cold-start lock-times by nearly an order of magnitude.

Fahim U. Rahman [ISSCC]

Techniques for "learning around" largely-static memory errors caused by aggressive memory-voltage overscaling, demonstrated on a low-power DNN accelerator SoC.

Sung Kim

RF1: Single-phase resonant clocked ASIC with programmable operating frequency of 0.8GHz-1.2GHz

Visvesh Sathe [CICC, JSSC]

A highly-multiplexed, delta-encoded mixed-signal biopotential recording architecture with common and differential-mode artifact suppression.

William A. Smith [VLSI Symp.]

A prototype demonstrating optimized ECoG signal chain design with reduced noise and ADC requirements, resolved from specific characteristics of ECoG signals.

William A. Smith [ESSCIRC] [TBIOCAS]

The first demonstration of truly voltage-scalable quasi-resonant clocking.

Fahim U. Rahman [ISSCC]

RF2: The first-ever fully integrated resonant clocked datapath.

Visvesh Sathe [VLSI Symp, JSSC]